ECT 213

ECT 213 ECT 213 Digital Circuits Spring 2008

Instructor: Daniel Kohn (dekohn@ncat.edu)

Office Hours: (click here)

Course Policies: (click here)

Grades GradeWatch

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Required Text: Digital Electronics withVHDL by William Kleitz

Required Software: Simulation Software (save to desktop -> just click to run [java MUST be installed])

Simulation Manual

Java

Required Parts: Parts List (Will be available as a kit from NC A&T IEEE Student Chapter)

Course Outline:

Topics Reading Handouts Assignments
Lecture 1:
  Number Systems Chapter 1 Lecture 1(Original)
Lecture 1(as presented)
Assignment #1 - Number Systems
Due 1/15/08
Lecture 2:
  Digital Signals Lecture 2
Lecture 3:
  Logic Gates
  Truth Tables
  Boolean Equations Chapter 3 Lecture 3 Home Work 2
Due 1/22/2008
Lab 1:
  Digital Circuit Simulations Lab 1 Due End of Lab.
Lecture 4:
  Boolean Algebra
  Simplification Chapter 5 Lecture 4
Boolean Reduction Laws/Rules/Theorems Home Work 3
Due 1/31/2008
Lab 2:
  Combinational Logic Circuit Breadboard Video 1
Breadboard Video 2
Logic Probe Lab 2
Schematic Due Feb 5th at ~~start of lab end of lab~~ by 5pm.
Lecture 5:
  HW #3
Review for Test #1
  Tuesday during Lab Test 1 Review

Answers for Review
Test #1
  Thursday in class
Lab 3:
  1st Breadboard Circuit Lab 3
Schematic You will need tools (and breadboard if you have one) for this lab.

Review videos for Lab 2 before lab.

~~Due end of lab.~~ Start of next weeks lab.
Lecture 6:
  Go Over Test
Lab 4:
  2nd Circuit Lab 4 Start of next weeks lab.
Lecture 7:
  K-Maps Rules Home Work 4
Due 2/28/2008
Lab 5:
  K-Map Simplification Lab 5 ~~Start End of next lab (after spring break)~~.
Due start of lab Mar 18 (will NOT be accepted late).
Lecture 8:
  K-Maps (HW Review)
Lecture 9:
  Digital Logic Tricks
  XOR / XNOR Lecture 9 HW (From Lecture Notes) Example 15 (page 13), Example 17 (Page 15), Example 10 (page 23) and Example 11 (Page 24)

Due Tuesday Mar 18
Lab 6:
  Xor and Parity Lab 6 Due end of lab (Mar 18).
Test #2
  Thursday (Mar 20) in class K-map software*
Lab 7:
  Adders Lab 7 Due start of next weeks lab (Apr 1). Will NOT be accepted LATE!
Lecture 10:
  Binary Arithmetic Lecture 10
Lab 8:
  BCD Add/Subtract Circuit Lab 8 Due start of next weeks lab (Apr 8). Will NOT be accepted LATE!
Lecture 11:
  Adders
  Comparators
  Encoders/Decoders
  Mux/DeMux
Lecture 11
Lecture 12:
  Intro to Latches/Flip-Flops Lecture 12 (Simulations)
Review for Test #2
  Tuesday during Lab
Test #2
  Tuesday in LAB
Lab 9:
  BCD to 7-seg Disp Using two 74LS47 IC's, add a 7-segment display output to LAB 8 Must be demoed to instructor for credit.
Lab 10:
  4 bit counter Lab 10 Must be demoed to instructor for credit by 5pm Tues May 6.

* - To practice for the test download K-map software and install the software. Pick a K-map size (2 -> 4 variable) using the slider at the bottom of the window. Fill it the K-map with 1's and 0's (don't use *'s) and then work it yourself and press analyze to see the computer generated answer. See help for how to fill in k-maps using Truth Tables as well. Note that | is used instead of a bar to indicate a NOT.

Reference Links: TTL Data Book (ON-Semi 2.5 MB)

TTL Pocket Databook (TI 4.9 MB)